A Novel Routing Architecture for Field-Programmable Gate-Arrays
نویسندگان
چکیده
منابع مشابه
Testable Clock Routing Architecture for Field Programmable Gate Arrays
Abstract This paper describes an efficient methodology for testing dedicated clock lines in Field Programmable Gate Arrays (FPGAs). A H-tree based clocking architecture is proposed along with a test scheme. The Htree architecture provides optimal clock skew characteristics. The H-tree architecture consumes at least 25% less of the routing resources when compared to conventional clock routing sc...
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تاریخ انتشار 2008